1. Field of the Invention
The present invention relates to a method for fabricating a thin film transistor used in a liquid crystal display or the like.
2. Description of the Related Art
FIG. 7 is a plan view of a conventional thin film transistor (hereinafter referred to as a TFT) having a staggered structure.
In FIG. 7, on the surface of an insulating substrate 51, a semiconductor layer 52 which is described below is formed. A gate insulating film (not shown) is formed so as to cover the surface of the semiconductor layer 52. The gate insulating film insulates a gate electrode 53 which will be formed in a later step from the semiconductor layer 52. On the surface of the gate insulating film, the gate electrode 53 is formed so as to cross the center portion of the semiconductor layer 52. A portion of the semiconductor layer 52 directly under the gate electrode 53 serves as a semiconductor-layer channel region 52c. One of the portions of the semiconductor layer 52 which are separated by the channel region 52c serves as a semiconductor-layer source 52a and the other portion serves as a semiconductor-layer drain 52b. At positions corresponding to the semiconductor-layer source 52a and the semiconductor-layer drain 52b, contact holes 56 and 57 for the connection to a source electrode 54 and a drain electrode 55 are formed in the gate insulating film, respectively. At a position in the gate electrode 53 opposite to the crossing portion in which the gate electrode 53 and the semiconductor layer 52 are crossed, a contact hole 59 for connecting the gate electrode 53 to a gate bus line 58 is formed. A TFT having the above-described structure is fabricated by the following method. The fabrication method will be schematically described with reference to FIGS. 8A through 8C.
First, as shown in FIG. 8A, a semiconductor layer 52 is formed on a transparent insulating substrate 51. Then, so as to cover the semiconductor layer 52, a gate insulating film (not shown) is formed.
Next, as shown in FIG. 8B, a gate electrode 53 is formed by patterning on the surface of the gate insulating film so as to cross the semiconductor layer 52.
Next, using the gate electrode 53 as a mask, an impurity element 60 is implanted from the gate insulating film side into the semiconductor layer 52 in a self-aligned manner, so as to form a semiconductor-layer source 52a and a semiconductor-layer drain 52b.
Next, an interlayer insulating film (not shown) is formed so as to cover the semiconductor layer 52 and the gate electrode 53.
Thereafter, as shown in FIG. 8C, a contact hole 61 for the connection to a source bus line or a source electrode (both not shown) is formed in the interlayer insulating film at a position corresponding to the semiconductor-layer source 52a. A contact hole 62 for the connection to a drain electrode (not shown) is formed in the interlayer insulating film at a position corresponding to the semiconductor-layer drain 52b. At the same time, a contact hole 63 for connecting the gate electrode 53 to a gate bus line (not shown) is formed in the interlayer insulating film at a position corresponding to the end portion of the gate electrode 53 on the opposite side to the crossing portion in which the gate electrode 53 and the semiconductor layer 52 are crossed.
Finally, a conductive material such as a metal is deposited on the interlayer insulating film and on the semiconductor-layer source 52a, the semiconductor-layer drain 52b, and the gate electrode 53 via the respective contact holes 61, 62, and 63. As a result, the contact holes 61, 62, and 63 are filled with the conductive material. Then, various bus lines and electrodes are formed by patterning.
When such a staggered type polycrystalline silicon TFT is to be fabricated, in order to attain good transistor characteristics, the semiconductor-layer source and drain regions are formed by introducing an impurity element into the semiconductor layer in a self-aligned manner as described above.
The impurities can be introduced by thermal diffusion or ion implantation. By using thermal diffusion, the impurities are introduced from the surface of the semiconductor layer. By using ion implantation, impurity ions are implanted into the semiconductor layer. The ion implantation method provides a more precise control of total dopant concentration and a depth to which the impurities are implanted into the semiconductor layer. Moreover, when the ion implantation technique is used, impurities can be shallowly implanted into the semiconductor layer, and impurities can be implanted into a thin film. Furthermore, ion implantation can be performed at low temperatures, so that a TFT can be formed on a glass substrate which is inexpensive and easily made in a larger size. For the above reasons, ion implantation is most often used for introducing impurities into a semiconductor layer in the fabrication process of a TFT.
In the above-described fabrication process of the TFT, impurities are implanted using an ion beam having a diameter of only several millimeters by a conventional ion implantation apparatus. When the ions are to be implanted over a large substrate using the above conventional ion implantation apparatus, it is necessary to either move the substrate mechanically or scan the ion beam electrically over the substrate because the area of the substrate is large as compared to the diameter of the ion beam. The provision of a mechanical moving means for the substrate or an electrical scanning means for the ion beam causes a problem in that the ion implantation apparatus becomes complicated, large-sized and expensive.
One technique for solving the above problem and in which ions can be easily implanted into a large area is an ion shower doping method. According to this technique, ions generated by using a plasma discharge as the ion source are accelerated at a low voltage without mass separating them, and are implanted into a substrate which has been heated to a predetermined temperature in a shower-like shape. In the ion implantation in a shower-like shape, ions are implanted over the semiconductor layer at a time.
When a glass substrate which is inexpensive and is easy to make in a larger size is used as a transparent insulating substrate which is usually used in an image sensor or a liquid crystal display, it is preferable to set the temperature in the heating process at a temperature of 600.degree. C. or lower. At a temperature of 600.degree. C. or lower, however, it takes about 20 hours or more to perform the annealing for activation after the ion implantation by the ion shower doping, which causes a problem in that the fabrication process is very time consuming.
As a liquid crystal substrate becomes larger, it is necessary to lower the resistance of the gate electrode of the TFT and the gate bus line. In general, polycrystalline silicon or polycrystalline silicon into which impurities have been doped is used for the gate of the self-aligned type polycrystalline silicon TFT. If such a material is used for the gate bus line, the resistance of the material is too high. Therefore, the use of low-resistance metal material such as aluminum is considered as the gate electrode wiring material.
However, such a low-resistance metal material has a low melting point. Accordingly, when the material is exposed at a temperature of 450.degree. C. or higher, there arise problems of roughness of the metal-film surface, occurrence of protrusions, peeling-off of the metal film, and the like. Thus, the metal film could not resist the activation at 600.degree. C., so that it cannot be used in the TFT in which the impurity implantation is performed in a self-aligned manner.
Against the above-mentioned problems, a method which does not necessitate the activating annealing is disclosed in Japanese Patent Application No. 03-304573. According to this method, the hydrogen ion concentration in a material gas used as the plasma source in the ion shower doping is set to be 80% or more. With the assist of the high-concentration hydrogen ions, the impurity ions are self-activated in the polycrystalline silicon thin film during the ion implantation. Accordingly, the annealing step after the ion implantation is not required, and it is possible to use the low-resistance metal material as the gate electrode interconnection material.
However, the above-described conventional ion shower doping technique involves the following problems.
According to the ion shower doping method utilizing self-activation, it is necessary to implant a large amount of hydrogen ions. In such a case, excessive hydrogen ions may also be implanted into the semiconductor-layer channel region directly under the gate electrode, and hence the transistor characteristics of the TFT are deteriorated due to the influence of the hydrogen ions.
In the polycrystalline silicon TFT formed by the conventional ion shower doping method, it is necessary to terminate crystal defects or the like existing in the channel region by implanting an appropriate amount of hydrogen atoms, in order to stabilize the transistor characteristics of the TFT.